正好路过的高手来帮忙解释一下了(英文有点难)!! 英文, 高手, 帮忙, 解释

Solutions

将SOPC Builder生成的NIOSII处理器添加到QuartusII中的BDF文件并完成工程后,编译时出现以下错误:
1." Range of port "d_address" in connecting module definition "the_cpu" is wider than the range of the port in the macrofunction instantion"
2." Range of port "i_address" in connecting module definition "the_cpu" is wider than the range of the port in the macrofunction instantion"

请问哪位高手能指点一下!!

Stoneway

是不是模块的总线宽度与管脚的管度不一致了?

Solutions

应该查那里呢?我用之前自己做的另一个工程(编译成功的!)修改成与之配置完全相同的工程,编译时就成功了.现在两个工程完全一样,却一个OK,一个出现以上问题,实在不知道是哪里出了问题? 请大哥指点!

dream-sister

Error: Can't open encrypted VHDL or Verilog HDL file "F:/altera/last_all/system/car_monitor_system/car_monitor_system/cpu.v" -- current license file does not contain a valid license for encrypted file Error: Node instance "the_cpu" instantiates undefined entity "cpu" Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 80 warnings Error: Quartus II Full Compilation was unsuccessful. 2 errors, 80 warnings 我在start compilation时出现这样的问题,请问各位好心的哥哥姐姐是不是license的问题啊?谁有license,传给我一份好吗?我有急用,小妹这边谢了!邮箱:dream-sistertom.com