在uer_logic_interface中,直接加入几个port
port_name wide direction share or not type
address 15 input shared address
data 8 inout shared data
wr_n 1 input shared write_n
rd_n 1 input shared read_n
cs_n 1 input not shared chipselect_n
按下一步就可以了,
关于setup,hold ,wait ,这些时间参数要查sram芯片手册了。 |