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- UID
- 111907
- 性别
- 男
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library synopsys; --new library
use synopsys.attributes.all;
entity motorctrl is
port (clk:in std_logic;
reset:in std_logic;
speed_now:in std_logic_vector(7 downto 0);
target_speed:in std_logic_vector(7 downto 0);
th_speed:in std_logic_vector(7 downto 0);
pwme ut std_logic
);
end;
--define the signal_structure and flow of the device
architecture motorctrl_arch of motorctrl is
--define the signal_structure and flow of the device
signal cnt125:integer range 0 to 124;
signal cnt375:integer range 0 to 374;
signal cnt500:integer range 0 to 499;
signal dth:std_logic_vector(7 downto 0);
signal pwm:std_logic;
--user defined encoded state machine:phase
type phase_type is(phb1,phb2);
attribute enum_encoding of phase_type:type is
"0"& --phb1
"1"; --phb2
signal phase:phase_type;
--user define encoded state machine:speeding
type speeding_type is(upa,upb,dn,final);
attribute enum_encoding of speeding_type:type is
"00"& --upa
"01"& --upb
"10"& --dn
"11"; --final
signal speeding:speeding_type;
begin
--concurrent signal assignments
--motorcontrol
peed_machine:process(reset,clk)
begin
if reset='1' then speeding<=upa;
dth<="00000000";
elsif(clk'event and clk='1')then
dth<=target_speed - th_speed;
case speeding is
when upa=>
if(speed_now=target_speed)then
speeding<=final;
elsif(speed_now>target_speed)then
speeding<=dn;
elsif(speed_nowdth)then
speeding<=upb;
end if;
when upb=>
if(speed_now=target_speed)then
speeding<=final;
elsif(speed_nowdth)and(speed_nowtarget_speed)then
speeding<=dn;
end if;
when dn=>
if(speed_now=target_speed)then
speeding<=final;
elsif(speed_nowdth)and(speed_nowtarget_speed)then
speeding<=dn;
end if;
when final=>
if(speed_now=target_speed)then
speeding<=final;
elsif(speed_nowdth)and(speed_nowtarget_speed)then
speeding<=dn;
end if;
when others=>null;
end case;
end if;
end process;
phase_machine:process(reset,clk)
begin
if reset='1' then
cnt500<=0;
cnt375<=0;
cnt125<=0;
pwm<='0';
pwme<='0';
phase<=phb1;
elsif(clk'event and clk='1')then
pwme<=pwm;
case phase is
when phb1=>
case speeding is
when upa=>cnt375<=374;cnt125<=124;
cnt500<=499;pwm<='1';
when upb=>cnt500<=499;cnt375<=cnt375-1;
cnt125<=124;pwm<='1';
when dn=>cnt500<=499;cnt375<=cnt375-1;
cnt125<=124;pwm<='0';
when final=>cnt500<=cnt500-1;cnt375<=374;
cnt125<=124;pwm<='1';
when others=>null;
end case;
if(cnt375=0 or cnt500=0)then
cnt500<=499;
cnt375<=374;
phase<=phb2;
end if;
when phb2=>
case speeding is
when upa=>cnt375<=374;cnt125<=124;
cnt500<=499;pwm<='1';
when upb=>cnt500<=499;cnt375<=374;
cnt125<=125-1;pwm<='0';
when dn=>cnt500<=499;cnt375<=374;
cnt125<=125-1;pwm<='1';
when final=>cnt500<=cnt500-1;cnt375<=374;
cnt125<=124;pwm<='0';
when others=>null;
end case;
if(cnt125=0 or cnt500=0)then
cnt500<=499;
cnt125<=124;
phase<=phb1;
end if;
when others=>null;
end case;
end if;
end process;
出现错误:
Error:line 5:can not open VHDL"synopsys"
Error:line 149:VHDL syntax error:unexpected end-of-file -try using the
Text Editor's Syntax Coloring command to find the missing delimiter or
keword |
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