标签: SYNTHESIS
| 版块 | 作者 | 回复/查看 | 最后发表 | |
| 分享[Verilog Coding For Logic Synthesis] | FPGA/CPLD可编程逻辑 | oaktwig1001 2008-2-28 | 1 / 1412 | yashiro 2008-6-5 00:44 |
| FPGA Synthesis with the Synplify Pro Tool[下载] | vincent 2006-1-23 | 11 / 3618 | summerytyj 2008-2-25 19:55 | |
| [EBOOK]Synthesis And Optimization Of DSP Algorithms | DSP技术 | QUJIN628 2005-12-13 | 4 / 2637 | jyn1122 2006-7-4 20:23 |
| Quartus II Analysis & Synthesis 一个棘手的问题 | mxy_1984 2006-5-11 | 2 / 2930 | mxy_1984 2006-5-12 14:55 | |
| XILINX 发布ACCELDSP SYNTHESIS 8.1 工具加速DSP系统设计 | juliguo 2006-4-5 | 0 / 1092 | juliguo 2006-4-5 16:11 | |
| xilinxSynopsys(XSI) Synthesis and simulation Design Guide！ | vincent 2005-12-31 | 4 / 1415 | xiaohai 2006-1-12 09:25 | |
| [下载]Xilinx Synthesis and Implementation Strategies to Accelerate | panjian1 2005-12-9 | 2 / 1244 | rfapc 2006-1-5 10:23 | |
| [EBOOK]Synthesis And Optimization Of DSP Algorithms | DSP技术 | lcchen123 2005-12-5 | 0 / 1023 | lcchen123 2005-12-5 10:42 |
| vhdl的小程序编译通过,可在SYNTHESIS却有这个毛病! | FPGA/CPLD可编程逻辑 | yufeng0810 2005-11-10 | 0 / 1088 | yufeng0810 2005-11-10 17:51 |