标签: testbenches
| 版块 | 作者 | 回复/查看 | 最后发表 | |
| Writing Testbenches using SystemVerilog | FPGA/CPLD可编程逻辑 | oleafyOo 2008-4-7 | 1 / 708 | stone133 2008-4-7 17:58 |
| 连载：编写高效的测试设计（testbenches）(译) | vincent 2006-6-23 | 14 / 2545 | lonbus 2007-6-12 11:59 | |
| writing_testbenches第二版[下载] | ddong 2006-4-27 | 5 / 1179 | brucelee 2006-4-28 09:24 | |
| [下载]Writing Testbenches--Functional Verification of HDL Models | FPGA/CPLD可编程逻辑 | vincent 2006-4-19 | 0 / 1148 | vincent 2006-4-19 11:13 |
| [下载]Writing Testbenches | vincent 2006-4-3 | 8 / 1606 | phoenixfeng 2006-4-4 18:29 |