ut std_logic_vector(2 downto 0));
end entity jsq;
architecture behave of jsq is
signal tt:std_logic_vector(2 downto 0);
signal temp:std_logic;
begin
p1:process(bs)
begin
if bs'event then
temp<= '0';
else temp<='1';
end if;
end process p1;
p2:process(fsk)
begin
if temp='0'then
tt<="000";
elsif(fsk'event and fsk='1') then
tt<=tt+1;
end if;
q<=tt;
end process p2;
end architecture behave;| 欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) | Powered by Discuz! 7.0.0 |