以前师兄画的PCB有点小错误,但是现在只有PCB图迷失从加工厂家那回来的,我先去铜了,(开始为了避免干扰,旗舰以外的地方都不满了铜)然后直接改变旱盘的网络标号,(为了改变细线的连接不知能否这样叫)再就冲连线,仅限几个元件.最后我选中全快板子铺铜了,但是再自检查,出现错误的提示很多,我都不知道如何改,现在把错误贴出来,请各位大侠帮忙解决一下:其中之一的错误是:
Processing Rule : Width Constraint (Min=31.496mil) (Max=31.496mil) (Prefered=31.496mil) (Is on net -12V )
Violation Track (45212.598mil,37855.118mil)(45514.173mil,37855.118mil) TopLayer Actual Width = 59.055mil
Violation Track (45514.173mil,37855.118mil)(45720.472mil,37648.819mil) TopLayer Actual Width = 59.055mil
Violation Track (45362.205mil,40078.74mil)(45449.606mil,40078.74mil) TopLayer Actual Width = 31.496mil
Violation Track (45449.606mil,40078.74mil)(45452.756mil,40075.591mil) TopLayer Actual Width = 31.496mil
Violation Track (45365.354mil,39240.945mil)(45452.756mil,39240.945mil) TopLayer Actual Width = 31.496mil
Violation Track (46039.37mil,39003.937mil)(46129.134mil,39003.937mil) TopLayer Actual Width = 31.496mil作者: wang816qing 时间: 2005-7-15 20:21 标题: 续上面的帖子:错误之二
Processing Rule : Width Constraint (Min=31.496mil) (Max=31.496mil) (Prefered=31.496mil) (Is on net +12V )
Violation Track (46720.472mil,38416.535mil)(46720.472mil,39314.961mil) TopLayer Actual Width = 31.496mil
Violation Track (47141.732mil,39421.26mil)(47141.732mil,39696.85mil) TopLayer Actual Width = 31.496mil
Violation Track (46614.173mil,39314.961mil)(47035.433mil,39314.961mil) TopLayer Actual Width = 31.496mil
Violation Track (46546.457mil,38590.551mil)(46922.047mil,38214.961mil) TopLayer Actual Width = 31.496mil
Violation Track (45775.59mil,38590.551mil)(46546.457mil,38590.551mil) TopLayer Actual Width = 31.496mil
Violation Track (47141.732mil,39472.441mil)(47145.669mil,39468.504mil) TopLayer Actual Width = 31.496mil
Violation Track (47295.276mil,37858.268mil)(47362.205mil,37925.197mil) TopLayer Actual Width = 31.496mil
Violation Track (47195.276mil,37758.268mil)(47295.276mil,37858.268mil) TopLayer Actual Width = 31.496mil
Violation Track (47118.11mil,38035.433mil)(47295.276mil,37858.268mil) TopLayer Actual Width = 31.496mil
Violation Track (46078.74mil,38590.551mil)(46081.102mil,38592.913mil) TopLayer Actual Width = 31.496mil作者: wang816qing 时间: 2005-7-15 20:26 标题: 续 错误之三:
Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Violation between Pad DC1-4(46023.622mil,37992.126mil) MultiLayer and
Track (46023.622mil,37996.063mil)(46023.622mil,38000mil) TopLayer
Violation between Pad Q1-1(45787.402mil,38248.031mil) MultiLayer and
Track (45787.402mil,38236.221mil)(45787.402mil,38248.031mil) TopLayer
Violation between Track (45925.197mil,37996.063mil)(45929.134mil,37996.063mil) BottomLayer and
Track (45925.197mil,37996.063mil)(45925.197mil,38016.063mil) BottomLayer
Violation between Pad DC1-3(45925.197mil,37992.126mil) MultiLayer and
Track (45925.197mil,37996.063mil)(45929.134mil,37996.063mil) BottomLayer
Violation between Pad DC1-4(46023.622mil,37992.126mil) MultiLayer and
Track (46023.622mil,37992.126mil)(46023.622mil,37996.063mil) BottomLayer
Rule Violations :5
Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Violation between Pad DC1-4(46023.622mil,37992.126mil) MultiLayer and
Track (46023.622mil,37996.063mil)(46023.622mil,38000mil) TopLayer
Violation between Pad Q1-1(45787.402mil,38248.031mil) MultiLayer and
Track (45787.402mil,38236.221mil)(45787.402mil,38248.031mil) TopLayer
Violation between Track (45925.197mil,37996.063mil)(45929.134mil,37996.063mil) BottomLayer and
Track (45925.197mil,37996.063mil)(45925.197mil,38016.06
3mil) BottomLayer
Violation between Pad DC1-3(45925.197mil,37992.126mil) MultiLayer and
Track (45925.197mil,37996.063mil)(45929.134mil,37996.063mil) BottomLayer
Violation between Pad DC1-4(46023.622mil,37992.126mil) MultiLayer and
Track (46023.622mil,37992.126mil)(46023.622mil,37996.063mil) BottomLayer
Rule Violations :5
错误之六:Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )
Violation Polygon Arc (45094.488mil,37360mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45212.598mil,37655.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45212.598mil,37855.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45374.016mil,37437.008mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45559.055mil,37555.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45559.055mil,37555.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45459.055mil,37655.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45459.055mil,37655.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45514.173mil,37855.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45514.173mil,37855.118mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45120mil,38340mil) TopLayer Actual Width = 20mil
Violation Polygon Arc (45120mil,38440mil) TopLayer Actual Width = 20mil作者: wang816qing 时间: 2005-7-15 20:30 标题: 好象铺铜全错了,还有错误之六:
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Violation Pad Free-0(45370.079mil,40803.15mil) MultiLayer Actual Hole Size = 157.48mil
Violation Pad Free-1(49031.496mil,40803.15mil) MultiLayer Actual Hole Size = 157.48mil
Violation Pad Free-2(49023.622mil,37437.008mil) MultiLayer Actual Hole Size = 157.48mil
Violation Pad Free-3(45374.016mil,37437.008mil) MultiLayer Actual Hole Size = 157.48mil
Rule Violations :4