源程序如下library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl is
port(clk,spe,reset:in std_logic;
en: out std_logic);
end;
architecture behave of ctrl is
type states is(s3,s2,s1,s0);
signal current_state,next_state:states;
begin
com:process(spe,current_state,reset)
begin
if reset'event and reset='1' then
next_state<=s3;
en<='0';
else
case current_state is
when s0=> en <='0';
if spe='1' then next_state<=s0;
else next_state<=s1;
end if;
when s1=> en <='1';
if spe='1' then next_state<=s2;
else next_state<=s1;
end if;
when s2=> en <='1';
if spe='1' then next_state<=s2;
else next_state<=s3;
end if;
when s3=> en <='0';
if spe='1' then next_state<=s0;
else next_state<=s3;
end if;
end case;
end if;
end process;
synch: process(clk)
begin
if clk'event and clk='1' then
current_state<=next_state;
end if;
end process;
end behave;
但是提示"case current_state is"的这一行出错！
提示说
unsupported feature error:conditional statement in this region for signals not supported
请问怎么回事？作者: zxy041 时间: 2010-12-21 16:59
如果process里面改为
com:process(spe,current_state,reset)
begin
if reset'event and reset='1' then
next_state<=s3;
en<='0';
elsif current_state = s0 then en <='0';
if spe='1' then next_state<=s0;
else next_state<=s1;
end if;
elsif current_state = s1 then en <='1';
if spe='1' then next_state<=s2;
else next_state<=s1;
end if;
elsif current_state = s2 then en <='1';
if spe='1' then next_state<=s2;
else next_state<=s3;
end if;
elsif current_state = s3 then en <='0';
if spe='1' then next_state<=s0;
else next_state<=s3;
end if;
end if;
end process;
则提示
process clocking is too complex
吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖作者: zxy041 时间: 2010-12-21 17:05
如果process里面改为
com:process(spe,current_state,reset)
begin
if reset'event and reset='1' then
next_state<=s3;
en<='0';
elsif current_state = s0 then en <='0';
if spe='1' then next_state<=s0;
else next_s上海注册公司tate<=s1;
end if;
elsif current_state = s1 then en <='1';
if spe='1' then next_state<=s2;
else next_state<=s1;
end if;
elsif current_state = s2 then en <='1';
if spe='1' then next_state<=s2;
else next_state<=s3;
end if;
elsif current_state = s3 then en <='0';
if spe='1' then next_state<=s0;
else next_state<=s3;
end if;
end if;
end process;
则提示
process clocking is too complex
吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖吖
