总是出现如下警告
Xst:737 - Found 1-bit latch for signal <temp_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
结果是将我的temp和i综合称为latch，我用chipscope进行调试的时候，发现i和temp永远是0，即赋值赋不进去，在网上找了好久，也参考了xilinx的官方解释，
说是有不完整的if，但是我检查了好多遍，发现我已经将所有情况考虑到了啊？
代码如下，请高手们指点啊！！
always @(rst,cs,byte_done)
if (rst)
begin
i<=2'b00;
temp<=24'b000000000000000000000000;
end
else
begin
if (cs==data)
begin
if(byte_done==1)
begin
if(i==2'b00)
begin
temp[7:0]<=sr;
temp[23:8]<=temp[23:8];
i<=i+1;
end
else if(i==2'b01)
begin
temp[15:8]<=sr;
temp[23:16]<=temp[23:16];
temp[7:0]<=temp[7:0];
i<=i+1;
end
else if(i==2'b10)
begin
temp[23:16]<=sr;
temp[15:0]<=temp[15:0];
i<=i+1;
end
else
begin
temp<=temp; //qd
i<=i;
end
end
else
begin
temp<=temp; //qd
i<=i;
end
end
else if(cs==data_ack)
if(i==3)
begin
i<=2'b00;
temp<=temp;
end
else
begin
i<=i;
temp<=temp;
end
else
begin
i<=i;
temp<=temp;
end
end作者: liumeco 时间: 2011-1-2 23:34
