1#chaodayou
注意看文档, TEX, TC的清楚条件
TXE: Transmit Data Register Empty.
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TIEN bit =1 in the
USART_CR2 register. It is cleared by a write to the USART_DR register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
TC: Transmission Complete.
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIEN=1 in the USART_CR2 register. It is
cleared by a software sequence (a read to the USART_SR register followed by a
write to the USART_DR register).
0: Transmission is not complete
1: Transmission is complete
如果使用TXE的话，数据全部发送完了，最好把TEN能关掉。
