module gen_clk(inta,clk,outb); input inta,clk;//intainta,,inta inta output outb; reg outb; reg [3:0] count; reg temp1,temp2,temp3,temp4; initial begin count=0; end always@(posedge clk )begin count<=count+1; if(count==1) begin temp1<=inta; end else if(count==2) begin temp2<=temp1; end else if(count==3) begin temp3<=temp2; end else if(count==4) begin outb<=temp3; end end endmodule |
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