是不是CASE 语句不能这么用啊？为何我定义的key1、clk 编译完后只有一个输出引脚呢？
=============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aabc1 is
Port ( clk : in std_logic;
q : out std_logic;
key1 : in std_logic_vector(3 downto 0)
);
end aabc1;
architecture Behavioral of aabc1 is
SIGNAL TT: std_logic;
begin
PROCESS (key1,clk)
BEGIN
CASE key1 IS
WHEN "1111" => TT <= '0';
WHEN "1001" => TT <= '1';
WHEN OTHERS => TT <= '0';
END CASE;
IF (TT = '1') THEN
q <= '0';
END IF;
END PROCESS;
end Behavioral;
