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标题: 初学Verilog，实现秒计数器的程序 [打印本页]

作者: zxt20102 时间: 2011-10-21 20:38 标题: 初学Verilog，实现秒计数器的程序

初学Verilog，实现秒计数器的程序，觉得没错了，就是无法实现。急需大虾的帮忙，感谢感谢！

module shock_clock(clk,LED);
input clk;
output [7:0] LED;
reg[7:0] LED;
reg[3:0] data_led1,data_led2,data_led3,data_led4,led_data,seg_en;
reg[27:0] cnt;
reg[1:0] seg_data;
always @(posedge clk)
begin
if(cnt == 5000000)
  begin
if(data_led1 == 9)
begin
   data_led1 <= 0;
   if(data_led2 == 9)
   begin
   data_led2 <= 0;
   if(data_led3 == 9)
      begin
      data_led3 = 0;
      if(data_led4 == 9)
      begin
         data_led1 <= 0;
         data_led2 <= 0;
         data_led3 <= 0;
         data_led4 <= 0;
      end
      else data_led4 <= data_led4 + 1;
      end
   else data_led3 <= data_led3 + 1;
   end
   else data_led2 <= data_led2 + 1;
end
else data_led1 <= data_led1 + 1;
  end
else cnt <= cnt + 1;
end

[email=always@(posedge]always@(posedge[/email] clk)
begin
if(seg_data == 3)
  seg_data <= 0;
else seg_data <= seg_data +1;

case(seg_data)
  0:seg_en = 4'b1110;
  1:seg_en = 4'b1101;
  2:seg_en = 4'b1011;
  3:seg_en = 4'b0111;
  default: ;
endcase

case(seg_en)
  4'b1110:led_data = data_led1;
  4'b1101:led_data = data_led2;
  4'b1011:led_data = data_led3;
  4'b0111:led_data = data_led4;
  default: ;
endcase
case(led_data)
  0: LED = 8'hc0;
  1: LED = 8'hf9;
  2: LED = 8'ha4;
  3: LED = 8'hb0;
  4: LED = 8'h99;
  5: LED = 8'h92;
  6: LED = 8'h82;
  7: LED = 8'hf8;
  8: LED = 8'h80;
  9: LED = 8'h90;
  default: ;
endcase

end
endmodule

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