例化OSERDES后在modsim中功能仿真
ddr 4：1 并转串
怎么输出恒为低电平
IBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;----------------------------------------------
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
ENTITY ddr_se_io IS
PORT (
d1 : IN STD_LOGIC; -- clock 0 rising edge
d2 : IN STD_LOGIC; -- clock 0 falling edge
d3 : IN STD_LOGIC; -- clock 1 rising edge
d4 : IN STD_LOGIC; -- clock 1 falling edge
dout : OUT STD_LOGIC;
clk2X : IN STD_LOGIC; -- freq=2x
clk1X : IN STD_LOGIC; -- freq=x
reset : IN STD_LOGIC
);
END ddr_se_io;
ARCHITECTURE Behavioral OF ddr_se_io IS
BEGIN
