library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY cnt6 IS
PORT ( clock,aclr,clk_en: IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END cnt6;
ARCHITECTURE ONE OF cnt6 IS
signal cq:std_logic_vector(7 downto 0);
begin
process(clock,clk_en,aclr)
begin
if aclr='1'then cq<=(others=>'0');
elsif clock'event and clock='1'then
if clk_en='1'then
if cq<256 then cq<=cq+1;
else cq<=(others =>'0');
end if;
end if;
end if;
end process;
q1<=cq;
end one;
这个运行完后，会出现Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "q1[0]" is stuck at GND
Warning (13410): Pin "q1[1]" is stuck at GND
Warning (13410): Pin "q1[2]" is stuck at GND
Warning (13410): Pin "q1[3]" is stuck at GND
Warning (13410): Pin "q1[4]" is stuck at GND
Warning (13410): Pin "q1[5]" is stuck at GND
Warning (13410): Pin "q1[6]" is stuck at GND
Warning (13410): Pin "q1[7]" is stuck at GND
怎么办啊？？？？？
