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标题: 请求高手指点 [打印本页]
作者: anny1209 时间: 2005-11-5 11:34 标题: 请求高手指点
我编了这个程序运行的时候老是出同一个错误,不知道那里错了!小妹初次编程请各位高手指点一下吧!
library ieee;
use ieee.std_logic_1164.all;
entity ad8109 is
port(clk,ce,updata,datain,reset:in std_logic;
dataout
ut std_logic;
out8
ut std_logic_vector(7 downto 0));
end ad8109;
architecture struct of ad8109 is
component shift32
port(a,clk:in std_logic;
y
ut std_logic);
end component;
component sp
port(d,clk:in std_logic;
q
ut std_logic_vector(7 downto 0));
end component;
signal a:std_logic_vector(7 downto 0);
signal sw:std_logic;
begin
process(clk,ce,updata,reset)
begin
if reset='0' then
out8<="00000000";
dataout<='0';
elsif(clk'event and clk='0') then
if ce='0'then
if updata='1' then
u1:shift32 port map (datain,clk,sw);
dataout<=sw;
elsif updata='0' then
u2:sp port map (datain,clk,a);
out8<=a;
end if;
end if;
end if;
end process;
end struct;
出的错误是:
error:terminnation notification:error in d:\anny\ad8109.vhd prevent further processing
作者: fenglouto 时间: 2005-11-5 20:14
两个模块也贴上来啊,帮你调试看下。
作者: anny1209 时间: 2005-11-7 10:48
请谢谢您指点:
shift32.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity shift32 is
port(a,clk:in std_logic;
y
ut std_logic);
end shift32;
architecture arch of shift32 is
component dff
port(d,clk:in std_logic;
q
ut std_logic);
end component;
signal z:std_logic_vector(32 downto 0);
begin
z(0)<=a;
g1:for i in 0 to 31 generate
dffx:dff port map (z(i),clk,z(i+1));
end generate;
y<=z(32);
end arch;
sp.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity sp is
port(d,clk:in std_logic;
q
ut std_logic_vector(7 downto 0));
end sp;
architecture arch of sp is
signal temp:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if clk'event and clk='0' then
temp(0)<=d;
for i in 1 to 7 loop
temp(i)<=temp(i-1);
end loop;
end if;
end process;
q<=temp;
end arch;
dff.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk:in std_logic;
q
ut std_logic);
end dff;
architecture arch of dff is
begin
process(clk,d)
begin
if clk'event and clk='0' then
q<=d;
end if;
end process;
end arch;
作者: anny1209 时间: 2005-11-7 10:51
请您指点:
Dff.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk:in std_logic;
q
ut std_logic);
end dff;
architecture arch of dff is
begin
process(clk,d)
begin
if clk'event and clk='0' then
q<=d;
end if;
end process;
end arch;
sp.vhd
library ieee;
use ieee.std_logic_1164.all;
entity sp is
port(d,clk:in std_logic;
q
ut std_logic_vector(7 downto 0));
end sp;
architecture arch of sp is
signal temp:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if clk'event and clk='0' then
temp(0)<=d;
for i in 1 to 7 loop
temp(i)<=temp(i-1);
end loop;
end if;
end process;
q<=temp;
end arch;
shift32.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift32 is
port(a,clk:in std_logic;
y
ut std_logic);
end shift32;
architecture arch of shift32 is
component dff
port(d,clk:in std_logic;
q
ut std_logic);
end component;
signal z:std_logic_vector(32 downto 0);
begin
z(0)<=a;
g1:for i in 0 to 31 generate
dffx:dff port map (z(i),clk,z(i+1));
end generate;
y<=z(32);
end arch;
作者: jjkjjk 时间: 2005-11-7 11:10
到XILINX 去开个WEBCASE 吧。 应该会有工程师帮你看的。 我上次就有个叫SALLY帮我把问题找到了。
作者: anny1209 时间: 2005-11-7 14:57
谢谢!我试试看吧
作者: anny1209 时间: 2005-11-7 15:01
哪个网站的论坛啊,我在xilinx没有找到论坛啊?
不好意思,对这方面我刚开始接触,什么都不懂呢
作者: jjkjjk 时间: 2005-11-7 17:22
到下面这个地方去开
http://www.xilinx-china.com/support/clearexpress/websupport.htm
要先注册一下
作者: anny1209 时间: 2005-11-8 14:19
谢谢!我进去了!非常感谢!
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