我也遇到了同样的问题，请达人指点！

在网上下载的xilinx的sdram参考设计，发现使用synplify综合的。但是我用xst综合src目录下的vhdl源文件，会报告说：
WARNING:Xst:766 - D:/HITSXPersonal/XilinxDev/xsdram/src/sdrm.vhd line 238: Generating a Black Box for component .
WARNING:Xst:766 - D:/HITSXPersonal/XilinxDev/xsdram/src/sdrm.vhd line 245: Generating a Black Box for component .
WARNING:Xst:766 - D:/HITSXPersonal/XilinxDev/xsdram/src/sdrm.vhd line 250: Generating a Black Box for component .
WARNING:Xst:766 - D:/HITSXPersonal/XilinxDev/xsdram/src/sdrm.vhd line 254: Generating a Black Box for component .
WARNING:Xst:766 - D:/HITSXPersonal/XilinxDev/xsdram/src/sdrm.vhd line 260: Generating a Black Box for component .
........
然后就是ISE产生一个错误：
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com

发现是顶层设计文件中使用了
component CLKDLL
component IBUF
component BUFG
等等primitive，但是有使用
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
为什么还是认为综合成了黑箱子呢？而且最后还有一个错误，综合不了。这可是xilinx自己的参考设计阿。总不能只能用synplify综合吧？