“非阻塞赋值由它们被陈述的次序决定被执行的情况,考虑下面的例子: initial begin a <= 0; a <= 1; end When this block is executed, there will be two events added to the nonblocking assign update queue. The previous rule requires that they be entered on the queue in source order; this rule requires that they be taken from the queue and performed in source order as well. Hence, at the end of time-step 1, the variable a will be assigned 0 and then 1." 换句话说:“最后一个非阻塞赋值操作将赢得优先权。”
参考文献:
[1] IEEE P1364.1 Draft Standard For Verilog Register Transfer Level Synthesis
[2] IEEE Standard Hardware Description Language Based on the Verilog Hardware
Description Language, IEEE Computer Society, IEEE Std 1364-1995
[3] Clifford Cummings, "Correct Methods For Adding Delays To Verilog Behavioral
Models," International HDL Conference 1999 Proceedings, pp. 23-29, April 1999.
作者和联系方式 (外注:偷懒省略。总之“Mr. Cummings, a member of the IEEE 1364 Verilog Standards Group (VSG) since 1994”,虽然文章所涉很使我们感到“离”众书“叛道”,但其实是足够可信的【并且使我疑团大释,所以拿出来让使用Verilog的家伙一齐“开怀”,译文中太多错误和缺点请大家不吝指正!】。本文英文原文可以从下面的 web site下载: www.fpga.com.cn 或 www.sunburst-design.com/papers 。)