library ieee;
use ieee.std_logic_1164.all;
entity notetabs is
port (clk: in std_logic;
toneindex: out integer range 0 to 15);
end;
architecture one of notetabs is
   signal counter: integer range 0 to 3;
begin
cnt8:process(clk)
 begin
  if counter=3 then counter<=0;
elsif (clk'event and clk='1') then counter<=counter+1;
end if;
end process;
search : process(counter)
begin
case counter is
when 00 =>toneindex<=3;
when 01 =>toneindex<=3;
when 02 =>toneindex<=3;
when 03 =>toneindex<=3;
end case;
end process;
end;

警告:Ignored unnecessary INPUT pin 'clk'

怎么解决?有影响吗?