错误报告如下: Analyzing Entity (Architecture ). ERROR:Xst:827 - "C:/projects/qdq/qdq.vhd" line 46: Signal a cannot be synthesized, bad synchronous description. --> Total memory usage is 76764 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 2 ( 0 filtered) Number of infos : 0 ( 0 filtered)
程序如下: entity qdq is Port ( clk : in std_logic; rst : in std_logic; a1 : in std_logic; a2 : in std_logic; a3 : in std_logic; a4 : in std_logic; a5 : in std_logic; light1,light2,light3,light4,light5ut bit:='0'; cadeut std_logic_vector(3 downto 0):="0000"); end qdq;
architecture Behavioral of qdq is signal a:std_logic_vector(4 downto 0); signal scade:std_logic_vector(3 downto 0); begin process(rst,a1,a2,a3,a4,a5) --第 46行 begin if (rst'event and rst='1') then a<="00000"; elsif ((a1='1')and(a2='0')and(a3='0')and(a4='0')and(a5='0')and(scade=0)) then a<=a1&a2&a3&a4&a5; elsif ((a1='0')and(a2='1')and(a3='0')and(a4='0')and(a5='0')and(scade=0)) then a<=a1&a2&a3&a4&a5; elsif ((a1='0')and(a2='0')and(a3='1')and(a4='0')and(a5='0')and(scade=0)) then a<=a1&a2&a3&a4&a5; elsif ((a1='0')and(a2='0')and(a3='0')and(a4='1')and(a5='0')and(scade=0)) then a<=a1&a2&a3&a4&a5; elsif ((a1='0')and(a2='0')and(a3='0')and(a4='0')and(a5='1')and(scade=0)) then a<=a1&a2&a3&a4&a5; else a<="11111"; end if; end process;作者: xlnxfpga 时间: 2005-11-18 23:35