port(clk
ut bit);end ll;
architecture behave of ll is
begin
pa:process
begin
wait for 100 ns;
clk<='0';
wait for 100 ns;
clk<='1';
end process pa;
end behave;
但是编译时说不支持，我的max+plusII是10.0baseline
书上有下面一段代码
entity ll is
port(clkut bit);
end ll;
architecture behave of ll is
begin
pa:process
begin
wait for 100 ns;
clk<='0';
wait for 100 ns;
clk<='1';
end process pa;
end behave;
但是编译时说不支持，我的max+plusII是10.0baseline
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