process(ce,clk) begin if ce='0'then if clk'event and clk='0' then q(0)<=datain; for i in 1 to 31 loop q(i)<=q(i-1); end loop; dataout<=q(31); end if; end if; end process;
process(update) begin if update='0'then stmp<=q; end if; end process;
......
出的错误是：if clk'event and clk='0' then 这行
Error:Unsupported feature error:Conditional Statement in this region for signal not supported
当我把上面的process改成
......
process(ce,clk) begin if clk'event and clk='0' then if ce='0'then q(0)<=datain; ......
不是的，我的原理图上的意思是说，ce要在clk的前面，也就是只有ce满足条件才有clk发生的，我该怎么做？为什么我在maxplus ii中不能将dataout设为‘Z’?它老是出错，说ERROR: Asynchronous Contrnous Control "ce" for DFF is inittalizing the DFF to a value other than logic '0' or logic '1' 。为什么啊？
