源代码：

`timescale 1ns/10ps

module RAM_2048_8(data, addr, CS_b, OE_b, WE_b);
   parameter   word_size = 8;
   parameter   addr_size = 11;
   parameter   mem_depth = 128;
   parameter   col_addr_size = 4;
   parameter   row_addr_size = 7;
   parameter   Hi_Z_pattern = 8'bzzzz_zzzz;
  
   inout [word_size - 1:0]   data;
   input [addr_size - 1:0]   addr;
   input   CS_b, OE_b, WE_b;
  
   reg [word_size - 1:0] data_int;

   reg [word_size - 1:0] RAM_col0[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col1[mem_depth - 1:0]; 
   reg [word_size - 1:0] RAM_col2[mem_depth - 1:0];  
   reg [word_size - 1:0] RAM_col3[mem_depth - 1:0];   
   reg [word_size - 1:0] RAM_col4[mem_depth - 1:0]; 
   reg [word_size - 1:0] RAM_col5[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col6[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col7[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col8[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col9[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col10[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col11[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col12[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col13[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col14[mem_depth - 1:0];
   reg [word_size - 1:0] RAM_col15[mem_depth - 1:0];
  
   wire [col_addr_size - 1:0] col_addr = addr[col_addr_size - 1:0];
   wire [row_addr_size - 1:0] row_addr = addr[addr_size - 1:col_addr_size];
  
   assign data = ((CS_b) == 0 && (WE_b == 1) && (OE_b == 0))?data_int: Hi_Z_pattern;
  
   always @(data or col_addr or row_addr or CS_b or OE_b or WE_b)
      begin
          data_int = Hi_Z_pattern;
          if((CS_b == 0) && (WE_b == 0))
              case(col_addr)
                 0:RAM_col0[row_addr] = data;
                 1:RAM_col1[row_addr] = data;
                 2:RAM_col2[row_addr] = data;
                 3:RAM_col3[row_addr] = data;
                 4:RAM_col4[row_addr] = data;
                 5:RAM_col5[row_addr] = data;
                 6:RAM_col6[row_addr] = data;
                 7:RAM_col7[row_addr] = data;
                 8:RAM_col8[row_addr] = data;
                 9:RAM_col9[row_addr] = data;
                 10:RAM_col10[row_addr] = data;
                 11:RAM_col11[row_addr] = data;
                 12:RAM_col12[row_addr] = data;
                 13:RAM_col13[row_addr] = data;
                 14:RAM_col14[row_addr] = data;
                 15:RAM_col15[row_addr] = data;
             endcase 
       
          else if((CS_b == 0) && (WE_b == 1) && (OE_b == 0))
              case(col_addr)
                  0:data_int = RAM_col0[row_addr];
                  1:data_int = RAM_col1[row_addr];
                  2:data_int = RAM_col2[row_addr];
                  3:data_int = RAM_col3[row_addr];
                  4:data_int = RAM_col4[row_addr];
                  5:data_int = RAM_col5[row_addr];
                  6:data_int = RAM_col6[row_addr];
                  7:data_int = RAM_col7[row_addr];
                  8:data_int = RAM_col8[row_addr];
                  9:data_int = RAM_col9[row_addr];
                  10:data_int = RAM_col10[row_addr];
                  11:data_int = RAM_col11[row_addr];
                  12:data_int = RAM_col12[row_addr];
                  13:data_int = RAM_col13[row_addr];
                  14:data_int = RAM_col14[row_addr];
                  15:data_int = RAM_col15[row_addr];
                 
              endcase
      end

endmodule

实现了一个128x128的ＳＲＡＭ，确切地说是１２８行，每行有１６列，每列的宽度为８位．

一共是１６Ｋ的ＲＡＭ．

我在综合时发现慢得要死，后来居然发现需要１３，９００个ＡＬＭ！！！！

天哪！！！难道使用逻辑单元实现ＲＡＮ就那么费吗？？？？？？