打开ise，运行modelsim的时候出来这么多的错误，是怎么回事啊？请高人指点，急急急急急急急.... ，谢谢了先 # Loading work.test_bp_t_bp_v_tf # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # Loading work.test_bp # ** Warning: (vsim-3009) [TSCALE] - Module 'test_bp' does not have a `timescale directive in effect, but previous modules do. # Region: /test_bp_t_bp_v_tf/uut # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # Loading work.b # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) b.v(42): Instantiation of 'BUFG' failed. The design unit was not found. # Region: /test_bp_t_bp_v_tf/uut/ist # Searched libraries: # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # work # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) b.v(44): Instantiation of 'IBUFG' failed. The design unit was not found. # Region: /test_bp_t_bp_v_tf/uut/ist # Searched libraries: # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # work # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) b.v(65): Instantiation of 'DCM' failed. The design unit was not found. # Region: /test_bp_t_bp_v_tf/uut/ist # Searched libraries: # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "C:\Xilinx6.3\verilog\mti_se\XilinxCoreLib_ver". # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'unisims_ver' at "C:\Xilinx6.3\verilog\mti_se\unisims_ver". # No such file or directory. (errno = ENOENT) # work # Loading work.glbl # Error loading design作者: minnow918 时间: 2006-2-6 13:18
