我编了一个DES加密算法在XC2S200E上实现，当到达Map步骤时，提示出现如下错误：

ERRORack:18 - The design is too large for the given device and package.
   Please check the Design Summary section to see which resource requirement for
   your design exceeds the resources available in the device.
  

If the slice count exceeds device resources you might try to disable
   register ordering (-r).  Also if your design contains AREA_GROUPs, you may be
   able to improve density by adding COMPRESSION to your AREA_GROUPs if you
   haven't done so already.
  

NOTE: An NCD file will still be generated to allow you to examine the mapped
   design.  This file is intended for evaluation use only, and will not process
   successfully through PAR.
  

This mapped NCD file can be used to evaluate how the design's logic has been
   mapped into FPGA logic resources.  It can also be used to analyze
   preliminary, logic-level (pre-route) timing with one of the Xilinx static
   timing analysis tools (TRCE or Timing Analyzer).

怎么按照提示的步骤解决这个问题?