在上电到配置的时间里，可以设置为高电平或悬浮。在配置时，FPGA内部复位信号会通过异步复位把IO口变成低电平。具体看下面
A Low level applied to the HSWAP_EN input enables
pull-up resistors on User I/Os from power-on throughout
configuration. A High level on HSWAP_EN disables the
pull-up resistors, allowing the I/Os to float. As soon as
power is applied, the FPGA begins initializing its configuration
memory. At the same time, the FPGA internally asserts
the Global Set-Reset (GSR), which asynchronously resets
all IOB storage elements to a Low state.
