调制

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PL_QPSK IS
PORT(CLK :IN STD_LOGIC;
START :IN STD_LOGIC;
X :IN STD_LOGIC;
Y :OUT STD_LOGIC);
END PL_QPSK;
ARCHITECTURE BEHAV OF PL_QPSK IS
SIGNAL Q:INTEGER RANGE 0 TO 7;
SIGNAL XX:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL YY:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL F:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK='1' THEN
IF START='0' THEN Q<=0;
ELSIF Q=0 THEN Q<=1;F(3)<='1';F(1)<='0';XX(1)<=X;YY<=XX;
ELSIF Q=2 THEN Q<=3;F(2)<='0';F(0)<='1';
ELSIF Q=4 THEN Q<=5;F(3)<='0';F(1)<='1';XX(1)<=X;
ELSIF Q=6 THEN Q<=7;F(2)<='1';F(0)<='0';
ELSE Q<=Q+1;
END IF;
END IF;
END PROCESS;
Y<=F(0) WHEN YY="11" ELSE
F(1) WHEN YY="10" ELSE
F(2) WHEN YY="01" ELSE
F(3);
END BEHAV

解调

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pl_qpsk2 is
port(clk :in std_logic;
start:in std_logic;
x :in std_logic;
y ut std_logic);
end pl_qpsk2;
architecture behav of pl_qpsk2 is
signal q:integer range 0 to 7;
signal xx:std_logic_vector(2 to 0);
signal yyy:std_logic_vector(1 to 0);
signal yy:std_logic_vector(2 to 0);
begin
process(clk)
begin
if clk' event and clk='1' then
if start='0' then q<=0;
elsif q=0 then q<=1;yy<=xx;y<=yyy(0);
if x='0' then xx="001";
elsif xx<="000";
end if;
elsif q=2 then q<=3;
if x='0' then xx<=xx+"001";
end if;
elsif q=4 then q<=5;y<=yyy(1);
if x='0' then xx<=xx+"010";
end if;
elsif q=6 then q<=7;
if x='0' then xx<=xx+"011";
end if;
else q<=q+1;
end if;
end if;
end process;
process(yy)
begin
if clk='1' and clk' event then
if yy="101" then yyy<="00";
elsif yy="011" then yyy<="01";
elsif yy="010" then yyy<="10";
elsif yy="100" then yyy<="11";
elsif yyy<="00";
end if;
end if;
end process;
end behav;