Frequency-Synthesis Output Clock - CLKFX
The CLKFX output clock provides a clock with the following frequency definition:
CLKFX frequency = (M/D) × effective CLKIN frequency
In this equation, M is the multiplier (numerator) with a value defined by the
CLKFX_MULTIPLY attribute. D is the divisor (denominator) with a value defined by the
CLKFX_DIVIDE attribute. Specifications for M and D, as well as input and output
frequency ranges for the frequency synthesizer, are provided in the Virtex-4 Data Sheet.
The rising edge of CLKFX output is phase aligned to the rising edges of CLK0, CLK2X, and
CLKDV. When M and D to have no common factor, the alignment occurs only once every
D cycles of CLK0.[em06]作者: stone133 时间: 2006-3-27 19:48
lz有Virtex-4 Data Sheet吗？有的话给传一个吧？作者: outlaw 时间: 2006-3-27 20:06
BUFGCTRL – Internal Global Clock Buffer
Any BUFGCTRL can drive any DCM in the Virtex-4 device using dedicated global
routing. A BUFGCTRL can drive the DCM CLKIN pin when used to connect two
DCMs in series.
我也没有这样用过，不过你看这段话对你有帮助没？第一个DCM的输出是不是不满足第二个DCM输入的条件？作者: stone133 时间: 2006-3-28 16:00
In general, using
the CLKFX from the first DCM cascaded to the second DCM is not recommended, due to the amount of output jitter from the first DCM. 作者: BlueSeaHaiChao 时间: 2006-3-29 06:58
From p 29 of the DS302 v1.4 Virtex 4 Data Sheet: DC and Switching
Characteristics, the output clocks from the DCM in the *high frequency mode*
shows 210-280 MHz capable FX outputs (for the slower -10 device) to pick up
where the *low frequency mode* drops off. The input for the high frequency
mode can be as low as 50 MHz if the DFS mode is all that's used.
100 MHz in, 100*M/N out up to 280 MHz in the -10 device.
Check to make sure you're 1) working in HF mode and 2) you're not using the
standard outputs - just the DFS.
