源码: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity singt is port( clk : in std_logic; dout : out std_logic_vector(7 downto 0)); end; architecture dacc of singt is
component data_rom port( address : in std_logic_vector( 5 downto 0); inclock : in std_logic; q : out std_logic_vector(7 downto 0)); end component;
signal q1 : std_logic_vector(5 downto 0);
begin process(clk) begin if clk'event and clk='1' then q1<=q1+1; end if; end process;
u1 : data_rom port map(address=>q1,q=>dout,inclock=>clk);