请问各位高手：
我在在maxplus 2中编写vhdl程序，怎样调用已存在的元件阿？
列如
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_ADDER IS
PORT (AIN ,BIN,CIN: IN STD_LOGIC;
COUT , SUM : OUT STD_LOGIC);
END ENTITY F_ADDER;
ARCHITECTURE THREE OF F_ADDER IS
BEGIN
COMPONENT H_ADDER
PORT (A, B: IN STD_LOGIC;
C0,S0: OUT STD_LOGIC);
END COMPONENT;
COMPONENT OR2
PORT(A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END COMPONENT;
SIGNAL D,E,F: STD_LOGIC;
BEGIN
U1:H_ADDER PORT MAP(A=>AIN,B=>BIN,C0=>D,S0=>E);
U2:H_ADDER PORT MAP(A=>E, B=>CIN,C0=>F,S0=>SUM);
U3: OR2 PORT MAP(A=>D, B=>F ,C=>COUT);
END ARCHITECTURE THREE;
