我在编译工程时候，出现了这个很奇怪的问题：

Error: Can't open encrypted VHDL or Verilog HDL file "D:/dev1/cpu_0.v" -- current license file does not contain a valid license for encrypted file
Error: Node instance "the_cpu_0" instantiates undefined entity "cpu_0"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 190 warnings
 Error: Processing ended: Thu May 11 11:54:22 2006
 Error: Elapsed time: 00:00:05

请大虾指点。或者QQ讨论一下：156710231。谢谢！