数字信号处理应用
| 应用领域 | DSP算法 |
| 通用领域 | 自适应滤波、滤波和卷积、检测和纠正、谱估计和傅立叶变换 |
| 语音处理 | 编码和解码、加密和解密、语音识别和合成、扬声器识别、回声消除、人工耳蜗的信号处理 |
| 音频处理 | hi-hi编解码、噪声消除、音频平衡、环境声学仿真、混音和编辑、声音合成 |
| 图像处理 | 压缩和解压缩、旋转、图像传输与分解、图像识别、图像增强、人工视网膜的信号处理 |
| 信息系统 | 语音信箱、传真、调制解调器、移动电话、线路均衡器、数据加密和解密、数字通信和局域网、延拓频谱技术、无线局域网、广播电视、生物医学信号处理 |
| 仪表设备 | 波束成型、波形发生器、瞬态分析、稳态分析、科学仪器设备、雷达和声纳 |
由于FPGA的编程的灵活性，我们也可以采用资源共享的方式来得到一个串行的实现电路，如图XX所示，在图中可以看到，它消耗了两个二选一多路器、一个乘法器、一个加法器和一个寄发器。虽然多了两个二选一多路器和一个触发器，但是这资源比乘法器的资源还是节约了不少。但是它的速度就降下来了，通过开关Sel来控制，先做A1和A2的乘法，结果在时钟驱动下保留在寄存器中，然后翻转Sel，再做A3和A4的乘法，结果和上次运行的存放在寄存器中的结果做加法，在第二个时钟驱动下存储最终结果。这样共享用一个乘法器，速度相比第一种情况慢，好的地方就是节约了面积。但是需要提的是，即使是这样的共享式的实现速度也会比DSP专用芯片的软实现速度要快。
相比之下得出，采用专用的FPGA做DSP，不但可以在速度和面积上灵活调节，至少实现速度还是比专用的DSP要快一点。通常我们很多场合，专用DSP的使用还是如日中天，一个原因是我们专用的FPGA的做DSP的资源还不是很富足，二个原因是专用DSP的开发采用的是软件式开发，而FPGA采用的是硬件开发，这对很多工程师来讲还是会选择前者的，第三个原因是这个成本问题，毕竟传统的专用的DSP芯片比专用的FPGA芯片要便宜。
3.3.3DSP支持资源 各FPGA厂商对数字信号处理的资源支持还是比较强大的，这包括前面提到的在通信领域和图像处理领域提供的支持资源，有相关的IP核、相关的使用工具和一些参考设计方案，这里我们就不再重复，只是做一些补充。表Xilinx 其他DSP IP核
| 分类 | IP核 | 描述 |
| 滤波器 | CIC Compiler | The Xilinx CIC Compiler LogiCORE is a module for design and implementation of Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices |
| DUC/DDC Compiler | Digital Up/Down Converters (DUC/DDC) are important components in the signal processing chains of many digital communications systems. The Xilinx DUC/DDC Compiler LogiCORE provides users with means to rapidly implement these functions for a range of wireless interface standards based on system-level parameters. The core implementation is delivered through the Xilinx CORE Generator system, and is designed to take advantage of the advanced features of Xilinx FPGA devices | |
| FIR Compiler | The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The implementation method can be specified by the user, with a choice of Multiply-Accumulate or Distributed Arithmetic architectures. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow | |
| 变换 | Discrete Fourier Transform | The Discrete Fourier Transform (DFT) core has been specifically designed to meet the needs of the LTE standard, in terms of point sizes, low latency and resource requirements. |
| Fast Fourier Transform | The Fast Fourier Transform (FFT) is a computationally efficient algorithm for computing the Discrete Fourier Transform (DFT). The FFT Core can compute 8 to 65536-point forward or inverse complex transforms on up to 12 parallel channels. The input data is a vector of complex values represented as two's-complement numbers 8 to 34 bits wide or single precision floating point numbers 32 bits wide. The phase factors can be 8 to 34 bits wide. All memory is on-chip using either Block RAM or Distributed RAM. Three arithmetic types are available: full-precision unscaled, scaled fixed-point, and block-floating point. Several parameters are run-time configurable: the point size, the choice of forward or inverse transform, and the scaling schedule. Four architectures are available to provide a tradeoff between size and transform time | |
| LTE Fast Fourier Transform | The LTE Fast Fourier Transform LogiCORE(TM) implements all transform lengths required by the 3GPP LTE specification, including the 1536-point transform for 15 MHz bandwidths. The transform length, transform direction, cyclic prefix length and scaling schedule may be configured on a per-frame basis | |
| 调制 | DDS Compiler | The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences |
| 块运算 | Complex Multiplier | Complex multiplication is a basic DSP operation. All operands, as well as the results, are represented as signed two's-complement data. Operand widths and result widths are parameterizable. Operand widths up to 63 bits are supported |
| CORDIC | The Xilinx CORDIC LogiCORE is a module for generation of the generalized coordinate rotational digital computer (CORDIC) algorithm which iteratively solves trigonometric, hyperbolic and square root equations. The core is fully synchronous using a single clock. Options include parameterizable data width and control signals. The core supports either serial architecture for minimal area implementations, or parallel architecture for speed optimization. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow |
表Altera其他DSP IP核
| 分类 | IP核 |
| 算法 | Floating Point Megafunctions |
| 滤波和变换 | CIC Compiler |
| FFT/IFFT | |
| FIR Compiler | |
| FIR Compiler II | |
| 调制解调 | Numerically Controlled Oscillator Compiler |
| 欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) | Powered by Discuz! 7.0.0 |