library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(cin:in std_logic;
     a,b:in std_logic_vector(3 downto 0);
       sut std_logic_vector(3 downto 0);
      cout std_logic);
end adder;
architecture behav of adder is
signal temp:std_logic_vector(4 downto 0);
begin
   process(a,b,cin)
  begin
     temp<=('0'&a)+b+cin;
      if(temp(3 downto 0)>9 or (temp(4)='1')then
         s<=temp(3 downto 0)+6;
         co<='1';
   else
     s<=temp(3 downto 0);
     co<='0';
    end if;
  end process;
end behav;

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