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标题: ST SPC563M60汽车动力控制方案 [打印本页]

作者: rise_ming    时间: 2013-1-28 21:38     标题: ST SPC563M60汽车动力控制方案

ST公司的SPC563M60是32位基于PowerPC Book E兼容CPU的MCU,适用于汽车动力控制应用.
       SPC563M60的用户模式和经典的Power Architecture指令集兼容,具有增强的性能以改善在嵌入式系统中的应用,并具有支持DSP的其它指令,以及集成了增强的时间处理单元,增强排队功能的ADC等.本文主要介绍了SPC563M60的主要特性和方框图.

       SPC563M60L5 SPC563M60B2 32-bit Power Architecture based MCU for automotive powertrain applications

      The SPC563M60 series microcontrollers are system-on-chip devices that are built on Power ArchitectureTM technology and:

      Are 100% user-mode compatible with the classic Power Architecture instruction set
Contain enhancements that improve the architecture’s fit in embedded applications
Include additional instruction support for digital signal processing (DSP)
Integrate technologies such as an enhanced time processor unit, enhanced queued
analog-to-digital converter.

       SPC563M60器件特性:


       SPC563M60主要特性:

       Feature List
       High performance e200z3 core processor
       32-bit PowerPC Book E programmer’s model
       Variable Length Encoding Enhancements
       –Allows PPC instruction set to be optionally encoded in a mixed 16 and 32 bit        instructions
      –Results in smaller code size
       Single issue, 32-bit PowerPC Book E compliant CPU
       In-order execution and retirement
       Precise exception handling
       Branch processing unit
       –Dedicated branch address calculation adder
       –Branch acceleration using Branch Lookahead Instruction Buffer
Load/store unit
       –1 cycle load latency
       –Fully pipelined
       –Big and Little endian support
       –Misaligned access support
       –Zero load-to-use pipeline bubbles
       Thirty-two 64 bit general purpose registers (GPRs)
       Memory management unit (MMU) with 8-entry fully-associative translation look-aside
buffer (TLB)
       Separate instruction bus and load/store bus
       Vectored interrupt support
       Interrupt latency < 120 ns @80 MHz (measured from interrupt request to execution of
first instruction of interrupt exception handler)
       Non maskable interrupt input. For handling external events that must produce an
immediate response. Such as power down detection. (May not be recoverable)
       Critical Interrupt input. For external interrupt sources that are higher priority than
provided by the Interrupt Controller. (Always recoverable)
New ‘Wait for Interrupt’ instruction, to be used with new low power modes.
       Reservation instructions for implementing read-modify-write accesses
       Signal processing extension (SPE) APU
       –Operating on all 32 GPRs that are all extended to 64 bits wide
       –Provides a full compliment of vector & scalar integer and floating point arithmetic
       operations (including integer vector MAC & MUL operations) (SIMD)
       –Provides rich array of extended 64 bit loads and stores to/from extended GPRs
       –Fully code compatible with e200z6 core
       Floating point
       –IEEE 754 compatible with software wrapper
       –Scalar Single precision in hardware, double precision with software library
       –Conversion instructions between single precision floating point and fixed point
       –Fully code compatible with e200z6 core
       Long cycle time instructions, except for guarded loads, do not increase interrupt latency
       Extensive system development support through Nexus debug port
       Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
       3 master ports, 4 slave ports
       –Masters: CPU Instruction bus; CPU Load/store bus (Nexus); DMA
       –Slave: Flash; SRAM; Peripheral Bridge; calibration EBI
       32-bit internal address bus, 64-bit internal data bus
       Enhanced direct memory access (eDMA) controller
       32 channels support independent 8, 16 or 32 bit single value or block transfers
       Supports variable sized queues and circular queues
       Source and destination address registers are independently configured to postincrement or remain constant
       Each transfer is initiated by a peripheral, CPU, or eDMA channel request
       Each eDMA channel can optionally send an interrupt request to the CPU on completion
       of a single value or block transfer
       Interrupt controller (INTC)
       191 peripheral interrupt request sources, plus 165 reserved positions.
       Eight software setable interrupt request sources.
9-bit vector
       –Unique vector for each interrupt request source.


                                         图1.SPC563M60系列方框图




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