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标题: 请教下面的VHDL代码,为什么地址线连不上??? [打印本页]

作者: mage1982    时间: 2006-8-30 10:27     标题: 请教下面的VHDL代码,为什么地址线连不上???

请问下面的代码编译以后,为什么addr地址线总是连不上????


library IEEE;
use IEEE.std_logic_1164.all;


package instr is
 type instruction is (add, sub, lda, ldb, sta, stb, outa, xfr);
end instr;


use work.instr.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;


entity mp is
 port(instr : in instruction;
   addr : in integer;
   data : inout integer
  );
end mp;


architecture mp of mp is
begin
 process(instr, addr)
  type regtype is array(0 to 255) of integer;
  variable a, b : integer;
  variable reg : regtype;
 begin
  case instr is --select instr to execute
   when lda =>
    a := data; --load a accumulator
   when ldb =>
    b := data; --load b accumulator
   when add =>
    a := a + b;
   when sub =>
    a := a - b;
   when sta =>
    reg(addr) := a; --put a accum into reg array
   when stb =>
    reg(addr) := b; -- put b accum in to reg array
   when outa =>
    data <= a; --output a accum
   when xfr => --transfer b to a
    a := b;
  end case;
 end process;


end mp;


 


 


作者: newbeesile    时间: 2006-9-4 11:17

这是怎么编译过的呢?
作者: csz    时间: 2006-12-27 11:04

我这还有一个小程序,下面这个小程序段只是一个分频。但是编译总报错:error:line 22:file ......timer.vhd:unsupported feature error:non-locally-static attribute names supported.---不支持的特征错误:本地的静态属性名称不支持。 
请指教。 

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity timer is
port(clk:in std_logic;
s100ut std_logic);
end timer;

architecture arch of timer is
signal xishu120000:std_logic_vector(16 DOWNTO 0);
signal s100s:std_logic;
begin

fenpin:process(clk)
begin
if(clk'event and clk<='1')then
xishu120000<=xishu120000+"1";
elsif(xishu120000<="11101010011000000")then
xishu120000<="00000000000000000";
s100s<=not s100s;
end if;

s100<=s100s;
end process;
end arch;

作者: stone133    时间: 2006-12-27 18:17

把arch换个名字试试看

elsif(xishu120000<="11101010011000000")是不是有点问题?()中应该用==


作者: fflower    时间: 2007-1-15 15:01

if(clk'event and clk<='1')then

  if(xishu120000<="11101010011000000")then

     xishu120000<="00000000000000000";

       elsifxishu120000<=xishu120000+"1";

这样再 看一下


作者: chen.lsi    时间: 2007-1-16 15:20

    process ( clk ) begin
        if ( clk'event and clk = '1' ) then
            if ( xishu120000 = "11101010011000000") then
                xishu120000<="00000000000000000";
            else   
                xishu120000<=xishu120000+"1";            
            end if ;
        end if ;
    end process ;




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