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标题: [求助]关于FFT IPCORE的问题求助 [打印本页]

作者: wgu    时间: 2006-8-31 16:24     标题: [求助]关于FFT IPCORE的问题求助

    各位大侠,我用ise6和modelsim5.7xe,采用xilinx的fft核做一个128点fft,在布线后仿真时出现错误如下:

     Fatal: SDF files require Xilinx primitive library


     FATAL ERROR while loading design


     Error:Error loading design


     pausing macro execution


郁闷死了,求救。


作者: vincent    时间: 2006-9-4 10:27

请参看xilinx问题集

This error can occur for several reasons:
- Using ModelSim XE with a user-compiled SimPrim Library
- Using ModelSim XE/PE/SE and applying the SDF to an RTL (pre-synthesis) design

Using ModelSim XE with a User-compiled SimPrim Library
All of the Xilinx libraries are pre-compiled and installed with MXE. It is required that the pre-compiled libraries are used with MXE. If you have manually compiled the simulation libraries, you must re-install MXE or download the latest pre-compiled libraries from the Web and install them.

For information on obtaining the updated pre-compiled libraries, see (Xilinx Answer 10616).

Using ModelSim XE/PE/SE and Applying the SDF to an RTL (pre-synthesis) Design

The SDF file contains delay information for all the gates and wires in the netlist. However, for the simulator to account for those delays, the gate-level (structural/back-annotated) netlist that is written by the Xilinx netlister tools (NGD2VHDL/NGD2VER) must be used. If the SDF is used with an RTL design file, this error will occur.

Usually, this error is due to the Xilinx netlister tools renaming the top-level entity name when the "-te" option is used ("-tm" option for Verilog). (By default, the Xilinx netlister tools retain the top-level entity name as it appeared in the RTL design.)

There are two resolutions to this problem:
- Check the top-level entity/module name in the output VHDL/Verilog file generated by Xilinx, and change the instantiation in the test bench to match it.
- Ensure that the "-te" option ("-tm" for Verilog) is not used.

作者: PPschoon    时间: 2009-3-9 21:46

Ensure that the "-te" option ("-tm" for Verilog) is not used

其中的 the "-te" option ("-tm" for Verilog) 到底是什么选项?

怎么设置?






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