对元件进行例化就可以了，书上可以找到现成的例子.
比如底层是一十分频的分频器在顶层加以调用
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FB10 IS
PORT(
CK : IN STD_LOGIC;
OUT1 : OUT STD_LOGIC
);
END FB10;
ARCHITECTURE a OF FB10 IS
SIGNAL D: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL TEMP: STD_LOGIC;
BEGIN
PROCESS(ck)
????BEGIN
IF ck'EVENT AND ck='1'??THEN
IF D<4 THEN
D<=D+1;
ELSE D<="000";
TEMP<=NOT TEMP;
END IF;
END IF;
END PROCESS;
OUT1<=TEMP ;
END a;
顶层
ARCHITECTURE a OF FBCON IS
...
..
..
COMPONENT FB10
PORT(
CK : IN STD_LOGIC;
OUT1 : OUT STD_LOGIC
?????????? );
END COMPONENT;
begin
U2: FB10 PORT MAP(CK=>CON1,OUT1=>CON2);
...
...
end a;作者: hstaii@163.net 时间: 2004-5-25 16:53 标题: 请问怎样在顶层文件中使用多个子文件的输入输出端？
