library ieee;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity complex is
port ( din : in std_logic_vector(3 downto 0);--input signal
clk : in std_logic;--system clock
en : in std_logic;-- enable key
dout : out std_logic_vector(3 downto 0));--output signal??
end complex;
architecture atl of complex is
signal count : integer range 0 to 11;
signal flash : std_logic_vector(47 downto 0);
-- signal clk : std_logic_vector(1 downto 0);
begin
process(din)
begin
for i in 11 downto 0 loop
flash((i*4)+3 downto i*4)<=din;
end loop;
end process;
process(en)
begin
process (clk)
begin
if (clk'event and clk='1') then
if count=11 then
count<=0;
else count<=count+1;
end if;
case count is
when 0 => dout<=flash(0 to 3);
when 1 => dout<=flash(16 to 19);
when 2 => dout<=flash(32 to 35);
when 3 => dout<=flash(4 to 7);
when 4 => dout<=flash(20 to 23);
when 5 => dout<=flash(36 to 39);
when 6 => dout<=flash(8 to 11);
when 7 => dout<=flash(24 to 27);
when 8 => dout<=flash(40 to 43);
when 9 => dout<=flash(12 to 15);
when 10 => dout<=flash(28 to 31);
when others => dout<=flash(44 to 47);
end case;
end if;
????end process;
end process;
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