以下是代码片段: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY if_thn IS PORT ( current_state : IN std_logic_vector(8 DOWNTO 0); x,y,z : IN std_logic; state_out : OUT std_logic_vector(2 DOWNTO 0) ); END if_thn; ARCHITECTURE behavior OF if_thn IS CONSTANT s0 : std_logic_vector(8 DOWNTO 0) := "000000000"; CONSTANT s1 : std_logic_vector(8 DOWNTO 0) := "100000001"; CONSTANT s2 : std_logic_vector(8 DOWNTO 0) := "100000010"; CONSTANT s3 : std_logic_vector(8 DOWNTO 0) := "100000100"; CONSTANT s4 : std_logic_vector(8 DOWNTO 0) := "100001000"; CONSTANT s5 : std_logic_vector(8 DOWNTO 0) := "100010000"; CONSTANT s6 : std_logic_vector(8 DOWNTO 0) := "100100000"; CONSTANT s7 : std_logic_vector(8 DOWNTO 0) := "101000000"; CONSTANT s8 : std_logic_vector(8 DOWNTO 0) := "110000000"; SIGNAL output1 : std_logic; SIGNAL output2 : std_logic; SIGNAL output3 : std_logic; BEGIN PROCESS(current_state,x,y,z) BEGIN IF (current_state = s1) OR (current_state = s3) OR (current_state = s4) THEN output1 <= x; ELSIF (current_state = s0) OR (current_state = s2) OR (current_state = s5) THEN output2 <= y; ELSIF (current_state = s6) OR (current_state = s7) OR (current_state = s8) THEN output3 <= z; ELSE output1 <= '0'; output2 <= '0'; output3 <= '0'; END IF; END PROCESS; state_out <= output1 & output2 & output3; END behavior; |
图1:新建Quartus II工程
图2:给工程添加设计文件
图3:为工程指定设计目标器件
图4:IF语句综合出Latch的警告
欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) | Powered by Discuz! 7.0.0 |