程序如下:
为什么定义信号量REGL,可不可以在PROCESS(LOCK)中直接给输出量赋值
IF LOCK='1' AND LOCK'EVENT THEN Q<=D;
两种方法有何区别?
谢谢指点
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY STATEINT IS
PORT(
CLK,EOC: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(7 downto 0);
OE, ADDA,ALE,START: OUT STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
QQ:OUT INTEGER RANGE 15 DOWNTO 0);
END STATEINT ;
ARCHITECTURE a OF STATEINT IS
TYPE STATES IS (ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7);
SIGNAL CURRENT_STATE,NEXT_STATE: STATES:=ST0;
SIGNAL REGL: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK:STD_LOGIC;
BEGIN
......
PROCESS(LOCK)
BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;
END IF;
END PROCESS;
Q<=REGL;
END a;
