library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is port(
                      clk: in    std_logic;
                    count: inout std_logic_vector(15 downto 0)
            );
end counter;

architecture Behavioral of counter is
  begin
    process(clk)
    begin
     if (clk='1') and (clk'event) then
             count<=count+1; 
     end if;
    end process;
end Behavioral;

count<=count+1; count也是输入吧，定义成out，是不是不好啊，我自己觉得，我直接在modelsim上建一个工程，试了一下，定义成out，有语法错误