今天在看xilinx的官方手册ZedBoard-CTT-V14.1时发现手册中实验3.1 Adding soft IP in the PL to interface with the Zynq PS存在错误，按照它的提示是不能成功生成.bit文件的。
操作步骤30.Type the following text in the UCF file其给的text应改为：
# Connect to Push Button "BTNU"
NET axi_gpio_0_GPIO_IO_pin[0] IOSTANDARD=LVCMOS25 | LOC=T18;
# Connect to Push Button "BTNR"
NET processing_system7_0_GPIO_pin IOSTANDARD=LVCMOS25 | LOC=R18;
否则在planahead中生成.bit文件时或出现如下错误ERROR:Bitgen:342
附录A：官方给出的操作步骤30
# Connect to Push Button "BTNU"
NET axi_gpio_0_GPIO_IO_pin IOSTANDARD=LVCMOS25 | LOC=T18;
# Connect to Push Button "BTNR"
NET processing_system7_0_GPIO_pin IOSTANDARD=LVCMOS25 | LOC=R18;
附录B：具体错误提示：
ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow
附录C：本人的详细解决过程
其实Xilinx很重视用户体验，提供了完善的帮助信息，遇到错误时认真分析
错误提示，善于根据提示去分析、定位并解决问题
一、 分析及初步定位问题：
This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards(IOSTANDARD) that are not user-assigned设计中有未分配的引脚，或引脚电平标准为分配。设计中涉及到引脚分配的操作就是改写约束文件中的脚本信息实现的，所以问题就定 位在了所添加的约束信息
二、 整理解决思路：
1：对未正确分配的管脚进行正确分配
2、改变bitgen选项，允许其在存在引脚未或其IO逻辑电平标准没分配的情况下创建bitstream
三、 先采取思路1：查看了管脚约束是有些问题，输入大意了两个都分配成了T18，将第二个修改为R18后，仍然出现同样的问题，再三确定约束正确后采取思路 2：点击project manager中的Bitsream Settings,在more options 后面输入：-g UnconstrainedPins:Allow然后点击generate bitstream生成成功，出现如下警告：
WARNING:Bitgen:343 - This design contains pins which have locations (LOC) that
are not user-assigned or I/O Standards (IOSTANDARD) that are not
user-assigned. This may cause I/O contention or incompatibility with the
board power or connectivity affecting performance, signal integrity or in
extreme cases cause damage to the device or the components to which it is
connected. To prevent this warning, it is highly suggested to specify all
pin locations and I/O standards to avoid potential contention or conflicts
and allow proper bitstream creation.
WARNINGhysDesignRules:372 - Gated clock. Clock net
system_i/chipscope_icon_0_control0[13] is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNINGhysDesignRules:2452 - The IOB axi_gpio_0_GPIO_IO_pin[0] is either not
constrained (LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
hysDesignRules:372 - Gated clock. Clock net