标识符
包括语法保留的关键词、模块名称、端口名称、信号名称、各种变量或常量名称等。语法保留的关键词是不可以作为后面几种名称使用的，Verilog和VHDL的主要关键字如下：
Verilog关键词
always endmodule medium reg tranif0 and end primitive module release
tranif1 assign endspecify nand repeat tri attribute endtable negedge rnmos tri0
begin endtask nmos rpmos tri1 buf event nor rtran triand bufif0 for not
rtranif0 trior bufif1 force notif0 rtranif1 trireg case forever notif1 scalared
unsigned casex fork or signed vectored casez function output small wait
cmos highz0 parameter specify wand deassign highz1 pmos specparam weak0
default if posedge strength weak1 defparam ifnone primitive strong0 while
disable initial pull0 strong1 wire edge inout pull1 supply0 wor else input
pulldown supply1 xnor end integer pullup table xor endattribute join remos
task endcase large real time endfunction macromodule realtime tran
VHDL关键词
abs downto library postponed subtype access else linkage procedure then
after elsif literal process to alias end loop pure transport all entity map range
type and exit mod record unaffected architecture file nand register units
array for new reject until assert function next rem use attribute generate
nor report variable begin generic not return wait block group null rol when
body guarded of ror while buffer if on select with bus impure open
severity xnor case in or shared xor component inertial others signal
configuration inout out sla constant is package sra disconnect label port srl
除了以上这些保留的关键词不可以作为用户自定义的其他名称，verilog和VHDL还有以下的一些用户自定义命名规则必须遵循：
