//=============================================
//控制每个占空比的持续时间
//=============================================
reg [31:0] cnt0;
always @ (posedge clk)
begin
if(cnt0==(FREQUENCE/(2**WIDTH)))
begin
cnt0<=0;
state0<=state0+1'b1;
end
else
begin
cnt0<=cnt0+1'b1;
end
end
//=============================================
//控制占空比增大与减小
//=============================================
always @ (posedge clk)
begin
if(state0[WIDTH])
state1<=state0[WIDTH-1:0];
else
state1<=~state0[WIDTH-1:0];
end
//=============================================
//生成与state1进行大小比较的计数器cnt1
//=============================================
wire [WIDTH-1:0] time_over;
assign time_over={WIDTH{1'b1}};
reg [WIDTH-1:0] cnt1;
always @ (posedge clk)
begin
if(cnt1==time_over)
begin
cnt1<=0;
end
else
begin
cnt1<=cnt1+1'b1;
end
end