3.3 模型的VHDL实现 用VHDL实现的部分源代码如下:
t1<=not p2 and not p4 and x0 and p1;
t2<=not p3 and x1 and p2;
t3<=not p5 and x3 and p4;
t4<=not p6 and not p7 and p3 and p5;
t5<=not p8 and x5 and x6 and p6;
t6<=not p9 and not x2 and not x4 and p7;
t7<=not p6 and not x5 and p8;
t8<=not p1 and not x6 and p6 and p9;
np1<=t8 or (p1 and not t1);
np2<=t1 or (p2 and not t2);
np3<=t2 or (p3 and not t4);
np4<=t1 or (p4 and not t3);
np5<=t3 or (p5 and not t4);
np6<=t4 or t7 or(p6 and not t5 and not t8);
np7<=t4 or (p7 and not t6);
np8<=t5 or (p8 and not t7);
np9<=t6 or (p9 and not t8);
3.4 基于Max+PlusⅡ的并行控制器仿真
在MAX+PlusⅡ中经编译后进行功能仿真,仿真波形如图4所示。波形表明结果是正确的。