本卡采用Xilinx Virtex-6 HX565Tor HX380T FPGA(40 GTX(6.6Gbps)和24(11.13Gbps) GTH串行收发器)技术,提供8个通道的PCI Express Gen 2,四个SFP+连接器(40 Gbps),MoSys的带宽引擎®IC(576MB的多组1T-SRAM,带有串行10G接口和板载ALU),高达16 GB的DDR3 SO-DIMM,Q
本卡采用Xilinx Virtex-6 HX565Tor HX380T FPGA(40 GTX(6.6Gbps)和24(11.13Gbps) GTH串行收发器)技术,提供8个通道的PCI Express Gen 2,四个SFP+连接器(40 Gbps),MoSys的带宽引擎®IC(576MB的多组1T-SRAM,带有串行10G接口和板载ALU),高达16 GB的DDR3 SO-DIMM,QDR II,10个11.18 Gbps和10个6.6Gbps串行端口。板上FPGA夹层连接器(FMC)连同现成的固定-移动的融合模块,连接各种不同的功能板用于各种不同应用程序。 <IMG style="PADDING-BOTTOM: 0px; BORDER-RIGHT-WIDTH: 0px; LIST-STYLE-TYPE: none; MARGIN: 0px; PADDING-LEFT: 0px; PADDING-RIGHT: 0px; BORDER-TOP-WIDTH: 0px; BORDER-BOTTOM-WIDTH: 0px; BORDER-LEFT-WIDTH: 0px; PADDING-TOP: 0px; border-image: initial" title="[转载]173 Xilinx Virtex-6 HXT&n" name=image_operate_19011375695257643 alt="[转载]173 Xilinx Virtex-6 HXT&n" src="http://www.orihard.com/files/173-01.jpg" width=750 height=366 real_src="http://www.orihard.com/files/173-01.jpg" action-type="show-slide" action-data="http%3A%2F%2Fwww.orihard.com%2Ffiles%2F173-01.jpg"> |
Powered by Xilinx Virtex-6 HX565Tor HX380T FPGA (with 40 GTX (6.6Gbps) & 24 GTH (11.13Gbps) serial transceivers), this optical network card provides access to eight lanes of PCI Express Gen 2 , four SFP+ connectors (40 Gbps), MoSys Bandwidth Engine® IC (576Mb Multibank 1T-SRAM with Serial 10G Interface and onboard ALU), up to 16 GB of DDR3 SO-DIMM, QDR II, ten 11.18 Gbps Two SFP+ ports are powered by an external PHY chip (with Electrical Dispersion Compensation) supporting short range, medium range, and long range optical interfaces. Two additional SFP+ ports are connected directly to the GTH transceivers of the on-bo ard FPGA. <IMG style="PADDING-BOTTOM: 0px; BORDER-RIGHT-WIDTH: 0px; LIST-STYLE-TYPE: none; MARGIN: 0px; PADDING-LEFT: 0px; PADDING-RIGHT: 0px; BORDER-TOP-WIDTH: 0px; BORDER-BOTTOM-WIDTH: 0px; BORDER-LEFT-WIDTH: 0px; PADDING-TOP: 0px; border-image: initial" title="[转载]173 Xilinx Virtex-6 HXT&n" alt="[转载]173 Xilinx Virtex-6 HXT&n" src="http://www.orihard.com/files/173-02.jpg" width=814 height=358 real_src="http://www.orihard.com/files/173-02.jpg" action-type="show-slide" action-data="http%3A%2F%2Fwww.orihard.com%2Ffiles%2F173-02.jpg"> Features: <IMG style="PADDING-BOTTOM: 0px; BORDER-RIGHT-WIDTH: 0px; LIST-STYLE-TYPE: none; MARGIN: 0px; PADDING-LEFT: 0px; PADDING-RIGHT: 0px; BORDER-TOP-WIDTH: 0px; BORDER-BOTTOM-WIDTH: 0px; BORDER-LEFT-WIDTH: 0px; PADDING-TOP: 0px; border-image: initial" title="[转载]173 Xilinx Virtex-6 HXT&n" alt="[转载]173 Xilinx Virtex-6 HXT&n" src="http://www.orihard.com/files/173-03.jpg" width=738 height=431 real_src="http://www.orihard.com/files/173-03.jpg" action-type="show-slide" action-data="http%3A%2F%2Fwww.orihard.com%2Ffiles%2F173-03.jpg"> The base framework provides all the design files, device drivers and API to access the memory mapped registers inside the FPGA. It enables an end user to instantiate and control custom logic blocks through the GUI application.Another key feature of the base EFW is the capability to program and erase the G18 BPI memory on the HTG-V6H-x8PCIE through the PCIe interface at very high speeds. Integrating the Field Upgradable controller allows any user design to be field upgradeable through PCIe. It can also eliminate the need for the USB platform cable during the design and development phase. The base framework also provides the targeted (MIG generated) wrapper for the 1066Mbps (533MHz) DDR3 and 350MHz QDRII+ controllers. Memory mapped MDIO and I2C controllers are also integrated in the EFW to control and configure the PHYs and clock elements on HTG-V6H-x8PCIE module. EFW also serves as the evaluation platform for the 10G low latency and dual-mode 10G/1G Ethernet IP solutions. It allows the user to test the 1G and 10G Ethernet interface capabilities of the HTG-V6H-x8PCIE without any code development. User can then extend the Ethernet interfaces to user specific designs through the industry standard AXI4-Streaming interface. Full simulation libraries included in the EFW enables the user to simulate and test the Ethernet interfaces before licensing the solutions. EFW’s integrated (time limited) 4-channel 128-bit data path (@ 250MHz) block DMA controller along with the PCIe device drivers allows the user to implement and verify high speed data and packet applications on the HTG-V6H-x8PCIE module. Key Features · Framework includes module targeted and hardware verified RTL blocks for: o x8 PCIe Gen2 hard IP block with PCIe application interface and arbiter o AXI4-Lite master/arbiter for distributed control and configuration of various EFW blocks o Two 1066Mbps/533MHz DDR3 controllers o Two 350 MHz QDRII+ controllers o Field upgradeable flash (FUp) controller for in-system field upgrade of the FPGA image through PCIe interface o MDIO and I2C controllers o DRP controller for run-time control and configuration of the GTH Transcievers · Time limited (30min) synthesizable binaries and full simulation libraries for hardware verified Ethernet solutions up to 10Gbps: o 10Gbps Low Latency Ethernet using the SFP+ interface on the module o Dual Mode 10G/1G Ethernet using the SFP+ interface on the module · Time limited (30min) synthesizable binaries and full simulation libraries for hardware verifiedMulti-channel (4) 128-bit data path scatter-gather block DMA controller · All modules with industry standard AXI-4 streaming interface for data path and AXI-4 Lite interface for control, configuration and memory interface · Top level RTL interface wrapper for custom user design block for easy implementation of user logic · Linux device drivers and API for PCIe interface · A single unified GUI for entire EFW with scripting support |
欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) | Powered by Discuz! 7.0.0 |