小弟无能 15号前要交论文了 这2个程序现在一点都不会做  小弟拜求了 下面2个能帮忙就帮下吧  小弟给您磕头了

1、设计一只4×4的键盘，有键按下时，输出值为十六进制的0～F。

无键按下时,输出值为十六进制的FF.(注: 设计中包含键盘扫描,键盘去抖等部分内容,有条件者附仿真结果.) (25分)

2、要求设计一只比赛用的抢答器。抢答器具有要求为：清零，开始抢答，A抢答，B抢答共四个按键，分别对A、B抢答键计数，采用BCD码计数，计数范围为0～99。有清零按键按下时，对A、B两组计数器清零；开始抢答键按下后，如有A抢答键先按下、A组计数器加一，无论B抢答键是否按下，B组计数器保持不变，反之亦然；一次开始抢答键按下后，A组计数器或者B组计数器只能加一；抢答器用的时钟频率为32768Hz。试用VHDL语言设计此功能的抢答器。(注: 有条件者附仿真结果.) (20分)

看看吧，我也在写论文，晚上看看

你们这么早较论文吗？我们要2月份呢，也在赶，争取月底搞定

恩 楼上的大哥  只需要编程序就好了   第2个我最急了 小弟在这里跪谢了

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors.  Please refer to the
-- applicable agreement for further details.

-- Generated by Quartus II Version 5.1 (Build Build 176 10/26/2005)
-- Created on Fri Jan 12 21:32:18 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--  Entity Declaration

ENTITY ag IS
 -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 ORT
 (
  clk : IN STD_LOGIC;
  rest : IN STD_LOGIC;
  start : IN STD_LOGIC;
  a : IN STD_LOGIC;
  b : IN STD_LOGIC;
  aout : OUT STD_LOGIC_VECTOR(7 downto 0);
  bout : OUT STD_LOGIC_VECTOR(7 downto 0)
 );
 -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 
END ag;

--  Architecture Body

ARCHITECTURE ag_architecture OF ag IS

 
BEGIN
process(rest,clk)
variable counta,countax,countb,countbx:std_logic_vector(3 downto 0);
variable en:std_logic;
begin
 if(rest='0')then
  en:='0';
  counta:="0000";
  countax:="0000";
  countb:="0000";
  countbx:="0000";
  aout<=(others=>'0');
  bout<=(others=>'0');
 elsif(clk'event and clk='1')then
  if(start='0')then
   en:='1';
  elsif(en='1')then
   if(a='0' or b='0')then
    if(a='0')then
     if(counta="1001")then
      countax:=countax+1;
      counta:="0000";
     else
      counta:=counta+1;
     end if;
    else
     if(countb="1001")then
      countbx:=countbx+1;
      countb:="0000";
     else
      countb:=countb+1;
     end if;
    end if;
    en:='0';
    aout(7 downto 4)<=countax;
    aout(3 downto 0)<=counta;
    bout(7 downto 4)<=countbx;
    bout(3 downto 0)<=countb;
   end if;
  end if;
 end if;
end process;
   
   
END ag_architecture;
没有加去抖动，功能仿真过了，你看看行不行。见笑了

多谢你了 大哥  等我过了这门课再来拜谢您

[此贴子已经被作者于2007-1-13 12:35:27编辑过]