老版本的ISE中曾经有stateCAD这个组件,可以很方便地进行FSM的设计;从ISE11开始,不再直接支持使用stateCAD进行设计了(也有绕过去的办法,见http://forums.xilinx.com/xlnx/board/crawl_message?board.id=OTHER&message... ),使得我们在设计FSM时需要手动编写HDL代码。那如何快速把HDL代码转换为图形化的FSM状态转移图呢?利用ISE和ModelSim配合就行了。
首先,在ISE中编写FSM的代码:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module FSM(din,matched,clk);
input din,clk;
output reg matched;
reg[2:0] state;
parameter S0=8'd0,S1=8'd1,S2=8'd2,S3=8'd3,S4=8'd4;
always@(posedge clk) begin
case(state)
S0:begin
if (din == 1)
begin
state <= S1;
end
else
begin
state <= S0;
end
matched <= 0;
end
S1:begin
if (din == 0)
begin
state <= S2;
end
else
begin
state <= S0;
end
matched <= 0;
end
S2:begin
if (din == 1)
begin
state <= S3;
end
else
begin
state <= S0;
end
matched <= 0;
end
S3:begin
if (din == 1)
begin
state <= S4;
end
else
begin
state <= S2;
end
matched <= 0;
end
S4:begin
if (din == 0)
begin
state <= S0;
end
else
begin
state <= S1;
end
matched <= 1;
end
default:
begin
state <= S0;
matched <= 0;
end
endcase
end
endmodule
然后,配置ModelSim的路径,在ISE---Edit---Preference中更改: