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标题: 【晒FRAM铁电存储器样片】+ MB85RS64 试用心得之二：开始写程序 [打印本页]

作者: upc_arm 时间: 2014-8-20 23:39 标题: 【晒FRAM铁电存储器样片】+ MB85RS64 试用心得之二：开始写程序

本帖最后由 upc_arm 于 2014-8-20 23:41 编辑

使用

MSP430单片机，以 IO模拟方式驱动MB85RS64，可以正确读写MB85RS64,程序如下：

#include "Main.h"

/*
CS----P2.0
SO----P2.1
SI----P2.2
CLK---P2.3
*/

/*
CS----P1.0
WP----P1.5
HOLD--P1.6
*/

#define MB85RS64_CS_L P1OUT |= BIT0
#define MB85RS64_CS_H P1OUT &= ~BIT0

#define MB85RS64_WP_L P1OUT |= BIT5
#define MB85RS64_WP_H P1OUT &= ~BIT5

#define MB85RS64_HOLD_L  P1OUT |= BIT6
#define MB85RS64_HOLD_H  P1OUT &= ~BIT6

void LEDOn(unsigned int cnt);

//寄存器相关
#define MB85RS64_WREN    0x06//Set Write Enable Latch 0000 0110
#define MB85RS64_WRDI    0x04//Reset Write Enable Latch 0000 0100B
#define MB85RS64_RDSR    0x05//Read Status Register 0000 0101B
#define MB85RS64_WRSR    0x01//Write Status Register 0000 0001B
#define MB85RS64_READ    0x03//Read Memory Code 0000 0011B
#define MB85RS64_WRITE    0x02//Write Memory Code 0000 0010B

void Init_uart0()
{
  UCA0CTL1|=UCSWRST;
  UCA0CTL0&=~UC7BIT;//字符长度为8
  UCA0CTL1|=UCSSEL_2;//选择系统时钟
  UCA0BR0=0x6D;  //波特率为9600
  UCA0BR1=0;
  UCA0MCTL=0;//UCA0MCTL=UCBRS0;
  IE2=UCA0RXIE+UCA0TXIE;//开接收使能
  UCA0CTL1&=~UCSWRST;
  P1SEL|=BIT1+BIT2; //将P1.1 P1.2设为第二功能
  P1SEL2|=BIT1+BIT2;
}

void sendChar(unsigned char c)
{
while(!(IFG2&UCA0TXIFG));
UCA0TXBUF=c;
}

void sendStr(unsigned char *s)
{
   while(*s!='\0')
   {
            sendChar(*s);
            s++;
   }
}

void main(void)
{
  volatile unsigned int i;
  char uart_tx_buf[30];
  unsigned char rd_data;
  unsigned char rd;
  unsigned char rd_test = 0;

  WDTCTL = WDTPW + WDTHOLD;                // Stop watchdog timer

  WDTCTL = WDTPW + WDTHOLD;                // Stop watchdog timer
  P1OUT = 0x00;                            // P1 setup for LED & reset output
  P1DIR |= BIT0 + BIT5;                   //
  P1SEL = BIT1 + BIT2 + BIT4;
  P1SEL2 = BIT1 + BIT2 + BIT4;
  UCA0CTL0 |= UCCKPL + UCMSB + UCMST + UCSYNC;  // 3-pin, 8-bit SPI master
  UCA0CTL1 |= UCSSEL_2;                   // SMCLK
  UCA0BR0 |= 0x02;                         // /2
  UCA0BR1 = 0;                            //
  UCA0MCTL = 0;                            // No modulation
  UCA0CTL1 &= ~UCSWRST;                   // **Initialize USCI state machine**
  //IE2 |= UCA0RXIE;                         // Enable USCI0 RX interrupt

  Init_uart0();
  sendStr("Init\n");

  while(1)
  {
//Set Write Enable Latch
CLR_MB85RS64_CS;
Write(MB85RS64_WREN);
SET_MB85RS64_CS;

//Read
CLR_MB85RS64_CS;
Write(MB85RS64_RDSR);
rd_data=Read();
SET_MB85RS64_CS;
sprintf(uart_tx_buf,"stat1==0x%02X\n",rd_data);
sendStr(uart_tx_buf);

//Set Write Enable Latch
CLR_MB85RS64_CS;
Write(MB85RS64_WRDI);
SET_MB85RS64_CS;

//Read
CLR_MB85RS64_CS;
Write(MB85RS64_RDSR);
rd_data=Read();
SET_MB85RS64_CS;
sprintf(uart_tx_buf,"stat1==0x%02X\n",rd_data);
sendStr(uart_tx_buf);
DelayXms(1000);
  }

  /*
  while(1)
  {
//Read_data(0,&rd,1);
//sprintf(uart_tx_buf,"rd=0x%02X\n",rd);
//sendStr(uart_tx_buf);

Write_data(0,&rd_test,1);
rd_test++;

Read_data(0,&rd,1);
sprintf(uart_tx_buf,"rd=0x%02X\n",rd);
sendStr(uart_tx_buf);
DelayXms(1000);
  }
  */

  while(1)
  {
//Set Write Enable Latch
CLR_MB85RS64_CS;
Write(MB85RS64_WREN);
SET_MB85RS64_CS;

//Write Memory Code
CLR_MB85RS64_CS;
Write(MB85RS64_WRITE);
Write(0x00);
Write(0x00);
Write(rd_test);
rd_test++;
SET_MB85RS64_CS;

//Read
CLR_MB85RS64_CS;
Write(MB85RS64_READ);
Write(0x00);
Write(0x00);
rd_data=Read();
SET_MB85RS64_CS;

sprintf(uart_tx_buf,"rd=0x%02X\n",rd_data);
sendStr(uart_tx_buf);

DelayXms(1000);
  }

  /*while(1)
  {
CLR_MB85RS64_CS;
Write(MB85RS64_RDSR);
stat=Read();
SET_MB85RS64_CS;
sprintf(uart_tx_buf,"stat=%02X\n",stat);
sendStr(uart_tx_buf);
//printf("%02X\n",stat);
DelayXms(100);

CLR_MB85RS64_CS;
Write(MB85RS64_WREN);
SET_MB85RS64_CS;

CLR_MB85RS64_CS;
Write(MB85RS64_RDSR);
stat=Read();
SET_MB85RS64_CS;
sprintf(uart_tx_buf,"stat222=%02X\n",stat);
sendStr(uart_tx_buf);
DelayXms(100);

//Write Status Register
CLR_MB85RS64_CS;
Write(MB85RS64_WRSR);
Write(0x00);
SET_MB85RS64_CS;
//Read Status Register
CLR_MB85RS64_CS;
Write(MB85RS64_RDSR);
stat=Read();
SET_MB85RS64_CS;
sprintf(uart_tx_buf,"stat=%02X\n",stat);
sendStr(uart_tx_buf);
//printf("%02X\n",stat);
sendStr("NEXT\n\n");
DelayXms(3000);
  }

  */

  Test();
  while(1)
  {
CLR_MB85RS64_CS;DelayXms(1000);
SET_MB85RS64_CS;DelayXms(1000);
  }

}

/*

  while (!(IFG2&UCA0RXIFG));
  temp = UCA0RXBUF;

*/

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