LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jia IS
PORT(
CLK,A :IN STD_LOGIC;
DATA:IN STD_LOGIC_Vector (7 downto 0);
q: out STD_LOGIC_Vector (7 downto 0);
b :OUT STD_LOGIC);
END jia;
ARCHITECTURE rtl OF jia IS
signal arf : std_logic_Vector(7 downto 0);
BEGIN
PROCESS(CLK,A)
Begin
IF(CLK'EVENT AND CLK='1')THEN
IF (A'EVENT AND A='1') then
arf<= DATA; --A的上升沿来到后将DATA的值赋给arf
end if;
arf <= arf-1; --每个clk时钟arf递减1
q<=arf;
END IF;
END PROCESS;
b<='1' WHEN(arf = 0) else '0'; --当arf为零时输出一个高电平
END rtl;
编译提示ignored unnecessary input pin'A'
